Chip capacitor precursors, packaged semiconductors, and assembly method for converting the precursors to capacitors

ABSTRACT

A capacitive precursor ( 100 ) and packaged semiconductor devices therefrom includes a substrate ( 105 ), a plurality of electrically conductive material layers ( 111 - 118 ) stacked on the substrate ( 105 ). The plurality of electrically conductive layers ( 111 - 118 ) provide first and second patterns ( 200  and  250 ). The first patterns ( 200 ) each include at least a first pair of overlaying areas free of the electrically conductive material, and the second patterns ( 250 ) each include at least a second pair of overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. A plurality of dielectric layers ( 101 - 107 ) are interposed between neighboring electrically conductive material layers ( 111 - 118 ) for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

FIELD

Embodiments of the invention are related to integrated circuits (ICs),and particularly to chip capacitors and packaged semiconductors havingone or more chip capacitors therein.

BACKGROUND

Packaged semiconductors can be embodied as single die packages ormulti-chip packages. On example of single chip packages is a chip scalepackage (CSP).

Multichip packages include multichip modules (MCM) andSystem-in-a-Package or System in Package (SIP). As commonly used anddefined herein, a plurality of die mounted on the same plane (e.g. thecavity substrate) is referred to as a MCM, whereas vertically stackeddie stacking is referred to as a SIP.

The MCM or SIP performs all or most of the functions of an electronicsystem, such as the functions required by a cellular phone or musicplayer. An exemplary SIP generally comprises several chips, such as aspecialized processor, dynamic random access memory (DRAM), flashmemory, and passive components, such as resistors, capacitors and insome case inductors, all mounted on the same substrate (e.g. amulti-layer printed circuit board (PCB)). This means that a completefunctional unit can be built in a single multi-chip package, so that fewexternal components are needed for system operation.

In certain applications, packaged semiconductors need high valuecapacitors, such as for power supply decoupling to minimize switchingnoise in certain electronic systems. To realize such high valuecapacitors, conventionally, an embedded capacitor is used. Conventionalembedded capacitors are realized using a stack up structure comprising aplurality of stacked metal layers having dielectric layers therebetweenand via connections between the metal layers formed on a conventionalmulti-layer PCB substrate, such as FR4 or BT.

SUMMARY

This Summary is provided to comply with 37 C.F.R. §1.73, requiring asummary of the invention briefly indicating the nature and substance ofthe invention. It is submitted with the understanding that it will notbe used to interpret or limit the scope or meaning of the claims.

Conventional embedded stack up structure capacitors require aninterconnect be formed between the metal stack up layers for eachcapacitor plate, and thus require a plurality of interconnect steps. Inaddition, a step is needed to electrically connect the stack upcapacitor(s) to an electrically conducting (e.g. copper) layer on thePCB substrate (e.g. FR4). Therefore, the process to form conventionalstack up structure capacitors involves a large number of processingsteps. Moreover, the dielectric between the metal layers is generallythe dielectric substrate material (e.g. FR4) which is known to have arelatively low dielectric constant, thus requiring a wide metal area toachieve reasonable capacitance values.

Embodiments of the present invention substantially solve the problems ofincorporating discrete capacitors in the packaged semiconductor deviceby dropping a pre-formed capacitor precursor, which as defined herein isa multilevel metal structure having dielectric between the respectiveelectrically conductive (e.g. metal) layers, but lacks electricalconnection between the electrically conductive layers, onto a PCBsubstrate surface during assembly. The substrate surface can be a top orbottom surface of a multi-layer PCB, or embedded within one of thelayers the multi-layer PCB.

The dielectric layers can be high k dielectric layers which helps limitthe necessary area to realize a desired capacitance value.Alternatively, the dielectric layers can have a relatively low k value,but can provide high dielectric strength. After dropping one or morepre-formed capacitor precursors according to embodiments of theinvention onto or into the substrate, the metal layers of respectiveplates of the pre-formed capacitor precursor are electrically connectedby standard printed circuit board manufacturing comprising forming vias(e.g. by drilling holes) and filing the vias with an electricallyconductive material (e.g. copper). The filled vias also serve thepurpose of electrically connecting the capacitor plates to electricallyconductive contact regions on the substrate material, and can be drilledand filled along with other vias on the PCB.

DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross sectional depiction of a chip capacitive precursoraccording to an embodiment of the invention.

FIG. 1B is a cross sectional depiction of a chip capacitive precursoraccording to another embodiment of the invention further comprising afeed through adapted structure for routing electrical connectionsthrough the capacitive precursor and the capacitor formed therefrom.

FIGS. 2A and B show exemplary designs for odd electrically conductivelayers, such as the odd numbered layers shown in FIGS. 1A and B, and anexemplary design for even layers shown in FIGS. 1A and B, according toanother embodiment of the invention.

FIG. 3A shows a depiction of a single capacitor precursor showingelectrically conductive material free areas for accommodating drillholes or vias within for completing the chip capacitor during assemblyprocessing.

FIG. 3B shows a depiction of a plurality of capacitive precursors on acommon substrate that can be provided after dicing a larger structure,or in another embodiment as an un-diced structure, according to yet anembodiment of the invention.

FIG. 4 is a cross sectional depiction of a capacitor precursor followingdrilling to form vias, according to an embodiment of the invention.

FIG. 5A is a cross sectional depiction of a chip scale package (CSP)comprising an integrated circuit die and a pair of chip capacitors,according to an embodiment of the invention.

FIG. 5B is a cross sectional depiction of a system-in-package (SIP)comprising a plurality of integrated circuit die stacked on one anotherhaving a dielectric material therebetween. At least one of theintegrated circuit die coupled to chip capacitors according to anembodiment of the invention is disposed on a PCB surface.

FIG. 6A is a cross sectional depiction of a multi-chip module (MCM)comprising a plurality of integrated circuit die arranged on a surfaceof a multi-layer PCB substrate. The integrated circuit die are eachcoupled to diced embedded capacitors, according to an embodiment of theinvention.

FIG. 6B is a cross sectional depiction of a multi-chip module (MCM)comprising a plurality of integrated circuits arranged on a surface of amulti-layer PCB substrate. The integrated circuit die are each coupledto embedded chip capacitors, wherein the embedded capacitors occupy anentire layer of the PCB, according to an embodiment of the invention.

FIG. 7A-D provide steps with respective cross sectional views for anexemplary method according to an embodiment of the invention forassembling a packaged semiconductor having embedded capacitors.

DETAILED DESCRIPTION

The present invention is described with reference to the attachedfigures, wherein like reference numerals are used throughout the figuresto designate similar or equivalent elements. The figures are not drawnto scale and they are provided merely to illustrate the instantinvention. Several aspects of the invention are described below withreference to example applications for illustration. It should beunderstood that numerous specific details, relationships, and methodsare set forth to provide a full understanding of the invention. Onehaving ordinary skill in the relevant art, however, will readilyrecognize that the invention can be practiced without one or more of thespecific details or with other methods. In other instances, well-knownstructures or operations are not shown in detail to avoid obscuring theinvention. The present invention is not limited by the illustratedordering of acts or events, as some acts may occur in different ordersand/or concurrently with other acts or events. Furthermore, not allillustrated acts or events are required to implement a methodology inaccordance with the present invention.

As defined herein, a chip capacitor is a multilayer monolithic capacitorconstructed in chip form, with metallized terminations for each plate ofthe capacitor to facilitate direct bonding on hybrid integratedcircuits, such as those built on PCB substrates. As described above, oneor more preformed chip capacitor precursors are first fabricated.Precursors become completed capacitors during assembly byplacing/dropping the capacitive precursor on a PCB substrate surface oron a internal layer of a multi-layer PCB laminate substrate usingconventional assembly processing including drilling vias and filling thevias with an electrically conductive material (e.g. copper). To avoidconfusion, as used herein, the process to form the capacitive precursoris referred to as fabrication, while the processing to convert thecapacitor precursor to the chip capacitor after dropping onto the boardsubstrate is referred to herein as part of assembly processing.

In one embodiment of the invention, the substrate for the precursorcapacitor can be a PCB substrate, such as FR4 or BT, or a ceramicsubstrate, wherein one or more preformed chip capacitor precursors aregenerally preformed using a fabrication process comprising conventionalPCB manufacturing techniques. The capacitor precursor fabricated becomesa chip capacitor during assembly by dropping the precursor into or ontoa board and electrically connecting the electrically conducting (e.g.metal) layers together associated with each of the respective capacitorplates. In one embodiment, the capacitor precursor becomes a chipcapacitor in the assembly process using standard PCB manufacturingcomprising forming vias (e.g. by drilling holes in the capacitorprecursor) and filing the vias with an electrically conductive material(e.g. copper). The filled vias can also serve the purpose ofelectrically connecting the capacitor plates to electrically conductivecontact regions on the board substrate, and in one embodiment are bedrilled and filled along with other vias on the substrate.

In another embodiment of the invention, the substrate for the capacitiveprecursor to be fabricated can be an integrated circuit substrate (e.g.silicon wafer). In this embodiment, a plurality of chip capacitorprecursors are generally simultaneously fabricated using conventionalintegrated circuit fabrication techniques (e.g. metal and dielectricdeposition, and etching). The chip precursor fabrication process canoptionally include the formation of through substrate vias (TSVs). Aswith the PCB substrate fabrication embodiment for the chip capacitorprecursor, the fabricated integrated circuit substrate-based capacitorprecursor is dropped into (in the case of embedded) or onto a boardsubstrate surface and has its metal layers associated with respectiveplates of the capacitor electrically coupled by filing the vias with anelectrically conductive material (e.g. copper). The filled vias can alsoserve the purpose of electrically connecting the capacitor plates toelectrically conductive contact regions on the board substrate, and canbe filled along with other vias on the board substrate.

FIG. 1A is a cross sectional depiction of a chip capacitive precursor100 according to an embodiment of the invention. Capacitive precursor100 comprises a substrate 105, and a plurality of electricallyconducting layers (e.g. metal comprising or N+ or P+ layers) 111-118 anddielectric layers 101-107 thereon including respective dielectric layersbetween neighboring ones of the plurality of electrically conducting(e.g. metal comprising or P+ or N+) layers 111-118 for electricalisolation therebetween. In one embodiment, the plurality of electricallyconducting layers 111-118 can comprise alternating first and secondpatterns, such as pattern 200 shown in FIG. 2A and pattern 250 shown inFIG. 2B. Layers 112, 114, 116 and 118 provide a first pattern or firstpatterns which each include electrically conducting material-free areas120 which overlay electrically conducting layers 111, 113, 115 and 117.Layers 111, 113, 115 and 117 provide a second pattern or second patternswhich each include electrically conductive material-flee areas 119 whichoverlay metal comprising areas of the first pattern in layers 112, 114,116, and 118. Capacitive precursor 100 does not have any electricalconnection between any of the electrically conducting layers 111-118.

As described below, during assembly, further processing is performed oncapacitive precursor 100, including at least via filling. After droppingthe capacitive precursor 100 on a surface of or to be embedded within alayer of a multilayer PCB (e.g. FR4), a first via is formed in area 119and a second via is formed in area 120, wherein the vias are generallyfilled in assembly with a metal comprising material (e.g. plated withcopper) to complete the chip capacitor. In the completed chip capacitor,filled vias formed in areas 119 and 120 are used to electrically connecttogether layers 112, 114, 116, and 118 and 111, 113, 115 and 117, whichserves as a first capacitor plate and a second capacitor plate,respectively.

As noted above, in one embodiment, substrate 105 can be a multi-layerPCB substrate, such as polymer-based FR4 or BT, or a ceramic-basedsubstrate. In this embodiment, the chip capacitor precursor 100 isgenerally fabricated using a stack up structure having a dielectricadhesive material placed between the respective PCR layers, usingconventional PCB manufacturing techniques (e.g. drilling, filling). Inanother embodiment, substrate 105 is a conventional integrated circuitsubstrate (e.g. silicon wafer), wherein the chip capacitor or chipcapacitors is/are generally fabricated using conventional integratedcircuit fabrication techniques (e.g. deposition of dielectric and metaland etching (e.g. plasma etching or RIE).

The dielectric layers 101-107 can comprise a variety of dielectricmaterials. In certain embodiments, such as for certain embodiments ofthe laminate embodiment for the capacitive precursor, the dielectricmaterial is that of the PCB board, such as FR4 or BT (k of about 4.2 to4.8). In another embodiment, the dielectric layer comprises a materialhaving a k≧50, such as BNZ (Bi—Nb—Zn) which provides a k value of about170-220. In yet another embodiment, the dielectric material is a highdielectric strength material, particularly for high voltageapplications. FIG. 1B is a cross sectional depiction of a chipcapacitive precursor 150 according to an embodiment of the inventionfurther comprising a feed through adapted structure 123 for routingelectrical connections (e.g. pin routing) through the capacitiveprecursor and the capacitor formed therefrom. For example, theelectrically conductive material free common area defined by structure123 can be used for a pin routing interconnect that goes through thecapacitor structure, but is otherwise unrelated to the capacitiveprecursor or later completed capacitive structure. The area of thestructure 123 should generally be in the range of from 0.05 to 0.5 mm,such as 0.1 to 0.3 mm and the region around the drilled region designedto allow clearance and tolerancing for drill processing. The regionaround the drilled region generally includes a larger diameter vialanding area (e.g. 2 times the drill diameter).

FIGS. 2A and 2B show exemplary designs 200 and 250, respectively, forodd electrically conducting layers, such as layers 111, 113, 115 and117, and even layers, such as layers 112, 114, 116 and 118. Layers 111,113, 115 and 117 which will form one plate of the chip capacitor (afterassembly) can use the pattern (e.g. metal pattern) shown in FIG. 2A,using any one (or more than one) of the electrically conductive materialfree areas 120. Similarly, layers 112, 114, 116 and 118 which will formthe other plate of the chip capacitor (after assembly) can use thepattern (e.g. metal pattern) shown in FIG. 2B, using any one (or morethan one) of the electrically conductive material free areas 119. Forthe stack up embodiment, the area of the electrically conductivematerial free areas 119 and 120 are generally large enough toaccommodate drill holes within. The exemplary designs shown in FIGS. 2Aand 2B include optional feed through adapted structure 123 for routingelectrical connections through the capacitive precursor and thecapacitor formed therefrom.

In one embodiment, the electrically conductive material (e.g. metal)patterns, and the locations of electrically conductive material freeareas 119 and 120 and optionally electrically conductive material freearea 123 can be designed to match an intended metal interconnect patternon the board substrate the capacitive precursor will be dropped onto. Asdescribed below relative to FIG. 3B, the capacitive precursor cancomprise a plurality of capacitive precursors on a common substrate 350.In this embodiment, the location of the electrically conductive materialfree areas 119 and 120 and optionally electrically conductivematerial-free area 123 for each capacitor precursor can be designed tomatch an intended metal interconnect pattern on the board substrate, inwhich each of the capacitive precursors will be dropped onto.

The fabricated capacitive precursor can be diced into structurescomprising single capacitor precursors, diced into structures comprisinga plurality of capacitive precursors, or a combination of singlecapacitor precursors and a plurality of capacitive precursors. FIG. 3Ashows a depiction of a single capacitor precursor 300 showingelectrically conductive material-free areas 119 and 120 foraccommodating drill holes within. Typically, following fabrication, aplurality of single capacitor precursors 300 are generated by dicing.FIG. 3B shows a depiction of a plurality of capacitive precursors on acommon substrate 350 that can be provided after dicing a largerstructure (e.g. including other capacitive precursors), or in anotherembodiment as an un-diced structure. Capacitive precursor 350 comprisesfive (5) capacitor precursors 301, 302 and 303, 304 and 305, eachshowing electrically conductive material free areas 119 and 120 foraccommodating drill holes within. Capacitive precursors 304 and 305include optional feed through adapted structure 123 for routingelectrical connections through the capacitive precursor and thecapacitor formed therefrom.

FIG. 4 is a cross sectional depiction of a capacitor precursor 400following drilling or etching in the case of TSV processing to form vias119 and 120. In one embodiment, a multi-layer laminate is fabricatedusing a substrate layer stack up process. Vias 119 and 120 are shownextending from top to bottom of capacitor precursor 400. Followingdropping onto a board during assembly, the vias are generally platedwith a metal (e.g. copper) which connects the respective metal layersfor each plate of the chip capacitor, and the chip capacitor to anelectrically conductive trace on the board substrate.

FIG. 5A is a cross sectional depiction of a chip scale package (CSP) 500comprising an integrated circuit die 502. CSP 500 comprises a firstsubstrate 520, such as multi-layer laminate PCB substrate havingdielectric adhesive between the respective e layers, and a first metalcomprising interconnect material 506 on the top and bottom surface offirst substrate 520. Vias through first substrate 520 which are presentare not shown for simplicity. CSP 500 includes bond wires 532, moldcompound 538, and solder balls 546. Chip capacitors according to anembodiment of the invention 528, such as formed in assembly by capacitorprecursors 400 shown in FIG. 4 to form vias and filling the resultingvias with a metal (e.g. copper) are shown on the top surface and thebottom surface of the first substrate 520. As known in the art, drillingcan comprise conventional mechanical drilling or laser drilling methodsor the like. In one embodiment the chip capacitor 528 comprises adecoupling capacitor connected a power supply terminal for the die 502and a ground for the die 502.

FIG. 5B is a cross sectional depiction of a system-in-package (SIP) 550comprising a 3 die SIP configuration employing both wirebonding and flipchip bonding. SIP 550 comprises a first substrate 520, such asmulti-layer PCB substrate having dielectric adhesive between thesubstrate layers, and a first metal comprising interconnect material(not shown) on the first substrate 520. A plurality of integratedcircuit die shown as die 1, die 2 and die 3 are stacked on one another.SIP 500 includes bond wires 532, mold compound 538, flip-chip balls 542and solder balls 546. Chip capacitors according to an embodiment of theinvention 528, such as formed in assembly by drilling capacitorprecursors 400 shown in FIG. 4 to form vias and filling the resultingvias with a metal (e.g. copper) are shown on the top surface and thebottom surface of the first substrate 520. In one embodiment the chipcapacitor 528 comprises a decoupling capacitor connected a power supplyterminal for the SIP and a ground for the SIP.

FIG. 6A is a cross sectional depiction of a multi-chip module (MCM) 600comprising a plurality of integrated circuits 601 and 602 arranged on asurface of a multi-layer PCB substrate 620. The integrated circuit dieare each coupled to respective diced embedded capacitors 611 and 612which are disposed on the second layer of the substrate 620, accordingto an embodiment of the invention. Since embedded capacitors arepre-fabricated as described above, embedded capacitors 611 and 612 caninclude a high k dielectric material. The layers of the substrate 620can comprise a dielectric material, such as FR4. Through drilled vias618 filled with a metal (e.g. copper) couple metal 621 on the topside ofthe substrate 620 to metal 622 on the bottom side of the substrate andcomplete the precursor capacitor to become chip capacitors. The die 601and 602 are shown coupled to chip capacitors 611 and 612, respectively.

FIG. 6B is a cross sectional depiction of a multi-chip module (MCM) 650comprising a plurality of integrated circuits 651 and 652 arranged on asurface of a multi-layer PCB substrate 620. The integrated circuit dieare each coupled to embedded chip capacitors according to an embodimentof the invention 661, 662, 663, wherein the embedded capacitors occupyan entire layer of the PCB, the according to an embodiment of theinvention. A metal filled through drilled via 671 is shown whichprovides an electrical connection between the metal 621 on the top ofthe substrate and the metal 622 on the bottom of the substrate.

FIG. 7A-D provide steps with respective cross sectional views for anexemplary method according to an embodiment of the invention forassembling a packaged semiconductor having embedded capacitorspositioned within a layer of a multi-layer PCB substrate. The exemplarypackaged semiconductor is the MCM 600 shown in FIG. 6A. FIG. 7A shows amultilayer PCB substrate having cut out regions formed by removing boardmaterial in a portion of a layer of a multilayer laminate substrate.FIG. 7B shows a generally planar structure after dropping dicedprecursor capacitors according to an embodiment of the invention intothe cut out regions. FIG. 7C shows the structure after constructing abuild up layer including a surface pre-preg layer. FIG. 7D shows theresulting structure after drilling to form vias which when filled willprovide electrical contact to plates of the embedded capacitorcomponents. After metallization to fill the vias and form the top sidemetal on the substrate, dies are attached, and bond wires placed, resultin the formation of MCM 600 shown in FIG. 6A.

An exemplary method of assembling a packaged semiconductor according toan embodiment of the invention having one or more chip capacitors in atop or bottom surface of a PCB substrate is now described. The packagedsemiconductor comprises a PCB substrate, at least one integrated circuiton the PCB substrate, and at least one chip capacitor die having firstand second capacitor plates coupled to the integrated circuit on the PCBsubstrate. The first substrate can be multi-layer PCB and haveelectrically conductive contact regions thereon, generally on its topand bottom surface. The method comprises dropping at least onepre-formed capacitor precursor die according to an embodiment of theinvention and the integrated circuit die on the same or opposite sidesof the PCB substrate. If the pre-formed capacitor precursor die lacks atleast a first pair of vias for providing an electrical contact betweencapacitor plates of the chip capacitor, following dropping, at least afirst pair of vias are formed in the pre-formed capacitor precursor die.The first pair of vias are then filled with an electrically conductivematerial (e.g. plated with copper) to form the chip capacitor, whereinthe filling of the vias provides both an electrical contact between thecapacitor plates of the chip capacitor and the electrically conductivecontact regions on the top and generally also the bottom surface of thePCB substrate.

In one embodiment, alignment for the drill process to form the vias canbe an automated “blind” process. The blind alignment process isgenerally needed in the case of embedded capacitors according toembodiments of the invention. Positioning data for the particularpackaged semiconductor device including lateral and optionally verticalcoordinates relative to some reference on the PCB (a particular cornerof the board or a bushing in the board) for mechanical alignment to thevia landing locations for the respective capacitive precursors isstored. Drilling can proceed to drill the via landing locations based onthe stored positioning data. Drilling can be guided to the proper depthbased on vertical position coordinates.

In another embodiment of the invention, the drill process to form thevias can be a “sighted” process based at least in part on observablesurface features. The sighted process is generally possible when chipcapacitor precursors according to embodiments of the invention aredropped on the top or bottom of the board. As with the blind processdescribed above, drilling can be guided to the proper depth based onstored vertical position coordinates.

Depending on application, capacitive precursors according to embodimentsof the invention can be standardized designs or custom designed. In thecase of custom designs, given a desired capacitance value, areaavailable, and placement on or embedded in a board, custom capacitorprecursors can be designed to provide the desired capacitance value.

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample only, and not limitation. Numerous changes to the disclosedembodiments can be made in accordance with the disclosure herein withoutdeparting from the spirit or scope of the invention. Thus, the breadthand scope of the present invention should not be limited by any of theabove described embodiments. Rather, the scope of the invention shouldbe defined in accordance with the following claims and theirequivalents.

Although the invention has been illustrated and described with respectto one or more implementations, equivalent alterations and modificationswill occur to others skilled in the art upon the reading andunderstanding of this specification and the annexed drawings. Inparticular regard to the various functions performed by the abovedescribed components (assemblies, devices, circuits, systems, etc.), theterms (including a reference to a “means”) used to describe suchcomponents are intended to correspond, unless otherwise indicated, toany component which performs the specified function of the describedcomponent (e.g., that is functionally equivalent), even though notstructurally equivalent to the disclosed structure which performs thefunction in the herein illustrated exemplary implementations of theinvention. In addition, while a particular feature of the invention mayhave been disclosed with respect to only one of several implementations,such feature may be combined with one or more other features of theother implementations as may be desired and advantageous for any givenor particular application. Furthermore, to the extent that the terms“including”, “includes”, “having”, “has”, “with”, or variants thereofare used in either the detailed description and/or the claims, suchterms are intended to be inclusive in a manner similar to the term“comprising.”

The Abstract of the Disclosure is provided to comply with 37 C.F.R.§1.72(b), requiring an abstract that will allow the reader to quicklyascertain the nature of the technical disclosure. It is submitted withthe understanding that it will not be used to interpret or limit thescope or meaning of the following claims.

1. A capacitive precursor, comprising: a substrate; a plurality ofelectrically conductive material layers stacked on said substrate, saidplurality of electrically conductive material layers comprising firstand second patterns, wherein said first patterns each comprise at leasta first pair of overlaying areas free of said electrically conductivematerial, and said second patterns each comprise at least a second pairof overlaying areas free of said electrically conductive material,wherein said first pair of areas overlay areas of said second patternhaving said electrically conductive material and said second pair ofareas overlay areas of said first pattern having said electricallyconductive material, and a plurality of dielectric layers includingrespective ones of said plurality of dielectric layers betweenneighboring ones of said plurality of electrically conductive materiallayers, wherein said plurality of electrically conductive materiallayers are electrically isolated from one another by said dielectriclayers.
 2. The capacitive precursor of claim 1, wherein said substratecomprises a polymer or a ceramic printed circuit board (PCB).
 3. Thecapacitive precursor of claim 1, wherein said substrate comprisessilicon.
 4. The capacitive precursor of claim 1, wherein saidelectrically conductive material comprises at least one metal.
 5. Thecapacitive precursor of claim 1, wherein at least one of said pluralityof dielectric layers comprise a material having a k≧50.
 6. Thecapacitive precursor of claim 1, wherein said first pair of areas andsecond pair of areas are between 0.05 mm to 0.5 mm.
 7. The capacitiveprecursor of claim 1, wherein said first and second patterns bothfurther comprise at least one common overlaying area that is free ofsaid electrically conductive material.
 8. The capacitive precursor ofclaim 1, comprising a plurality of said capacitive precursors on saidsubstrate.
 9. The capacitive precursor of claim 8, wherein said firstand second patterns both further comprise at least one common overlayingarea that is free of said electrically conductive.
 10. A packagedsemiconductor device, comprising: a first printed circuit board (PCB)substrate; first electrically conductive interconnect material on saidfirst substrate; at least one integrated circuit die on said firstsubstrate coupled to said first interconnect; at least one chipcapacitor on a surface of said first substrate or embedded within saidfirst substrate, said chip capacitor comprising: a second substrate; aplurality of electrically conductive material layers stacked on saidsecond substrate, said plurality of electrically conductive materiallayers comprising first and second patterns, wherein said first patternseach comprise at least a first pair of overlaying areas free of saidelectrically conductive material, and said second patterns each compriseat least a second pair of overlaying areas free of said electricallyconductive material, wherein said first pair of areas overlay areas ofsaid second pattern having said electrically conductive material andsaid second pair of areas overlay areas of said first pattern havingsaid electrically conductive material; a plurality of dielectric layersincluding respective ones of said plurality of dielectric layers betweenneighboring ones of said plurality of electrically conductive layers;and at least a first pair of vias formed in said first pair of areasfree of said electrically conductive material filled with a secondelectrically conductive material which provides an electrical contactbetween said plurality of electrically conductive material layerscomprising said first pattern and said plurality of electricallyconductive material layers comprising said second pattern to providerespective capacitor plates of said chip capacitor, wherein said firstelectrically conductive material is coupled to contact regions of saidinterconnect material on said first electrically conductive material.11. The packaged semiconductor device of claim 10, wherein saidintegrated circuit die comprises a plurality of said integrated circuitdie stacked on one another, whereby said packaged semiconductor devicecomprises a system in package (SIP).
 12. The packaged semiconductordevice of claim 10, wherein said integrated circuit die comprises aplurality of said integrated circuit die in a coplanar arrangement on asurface of said first substrate, whereby said packaged semiconductordevice comprises a multi-chip module (MCM).
 13. The packagedsemiconductor device of claim 10, wherein said chip capacitor comprisesa decoupling capacitor connected a power supply terminal of saidintegrated circuit die and a ground for said integrated circuit die. 14.The packaged semiconductor device of claim 10, wherein said secondsubstrate comprises a polymer or a ceramic printed circuit board (PCB).15. The packaged semiconductor device of claim 10, wherein said secondsubstrate comprises silicon.
 16. The packaged semiconductor device claim10, wherein at least one of said plurality of dielectric layers comprisea material having a k≧50.
 17. The packaged semiconductor device claim10, wherein said chip capacitor is on said surface of said firstsubstrate.
 18. The packaged semiconductor device claim 10, wherein saidchip capacitor is embedded within said first substrate.
 19. The packagedsemiconductor device of claim 10, wherein said first and second patternsboth further comprise at least one common overlaying area that is freeof said electrically conductive material, wherein said common overlayingarea that is free of said electrically conductive material is filledwith said first electrically conductive material and is operable toprovide a through via connection between said first electricallyconductive interconnect material on a top surface of said firstsubstrate to a second electrically conductive interconnect material on abottom surface of said first substrate.
 20. A method of assembling apackaged semiconductor device comprising a first board substrate, atleast one integrated circuit die on said first substrate, and at leastone chip capacitor die having first and second capacitor plates coupledto said integrated circuit die on or embedded within said firstsubstrate, said first substrate having electrically conductive contactregions thereon, comprising: dropping a pre-formed capacitor precursoron a surface of said first substrate or within said first substrate;dropping said integrated circuit die on either of said first substrate;if said pre-formed capacitor precursor lacks at least a first pair ofvias for providing an electrical contact between capacitor plates ofsaid chip capacitor, following said dropping said pre-formed capacitorprecursor, forming at least a first pair of vias in said pre-formedcapacitor precursor; and filling said first pair of vias with anelectrically conductive material to form said chip capacitor, whereinsaid filling of said vias provides an electrical contact between saidfirst and second capacitor plates of said chip capacitor and saidelectrically conductive contact regions on said first substrate.
 21. Themethod of claim 20, wherein said pre-formed capacitor precursorcomprises: a second substrate; a plurality of electrically conductivematerial layers stacked on said second substrate, said plurality ofelectrically conductive material layers comprising first and secondpatterns, wherein said first patterns each comprise at least a firstpair of overlaying areas free of said electrically conductive material,and said second patterns each comprise at least a second pair ofoverlaying areas free of said electrically conductive material, whereinsaid first pair of areas overlay areas of said second pattern havingsaid electrically conductive material and said second pair of areasoverlay areas of said first pattern having said electrically conductivematerial; a plurality of dielectric layers including respective ones ofsaid plurality of dielectric layers between neighboring ones of saidplurality of metal layers; and wherein said plurality of electricallyconductive material layers are electrically isolated from one another bysaid dielectric layers.
 22. The method of claim 21, wherein said secondsubstrate comprises a printed circuit board (PCB) substrate having aplurality of laminate layers, wherein said method includes said formingstep, said forming step comprising drilling.
 23. The method of claim 22,wherein an entire one of said at least one of said plurality of laminatelayers for said PCB is provided by said pre-formed capacitor precursor.24. The method of claim 20, wherein said pre-formed capacitor precursorcomprises at least one pre-formed capacitor precursor die.
 25. Themethod of claim 20, wherein said second substrate comprises a printedcircuit board (PCB) substrate having a plurality of laminate layers, andsaid pre-formed capacitor precursor die is embedded in at least one ofsaid plurality of laminate layers.
 26. The method of claim 21, whereinsaid second substrate comprises an integrated circuit substrate.
 27. Themethod of claim 26, wherein said integrated circuit substrate comprisessilicon.
 28. The method of claim 21, wherein at least one of saidplurality of dielectric layers comprise a material having a k≧50. 29.The method of claim 20, wherein said forming said vias comprisesdrilling.
 30. The method of claim 29, wherein said drilling is guided atleast in part by stored position data for said packaged semiconductordevice.
 31. The method of claim 29, wherein said drilling is guided atleast in part by an on observable surface feature.